1. Field of the Invention
The invention relates to a clock switching circuit, and in particular relates to a glitch-free clock switching circuit and method thereof.
2. Description of the Related Art
Due to improved integrated circuit technology, increased integrated circuit application and consumer demand, more and more circuits are being required within an integrated circuit. As a result, one important issue for integrated circuit designers is the control of power consumption, of which, the clock switching circuit plays an important role. Generally, computer systems or communication systems have a plurality of clock signals with different frequencies. For example, some applications require very high frequency signals and other applications require low frequency signals. Thus, to efficiently control system performance and power consumption, the system usually uses clock switching circuits to change different clock signal frequencies for different applications.
FIG. 1 shows a conventional clock switching circuit. The clock switching circuit can be a multiplexer. The multiplexer receives clock signals CLK_A and CLK_B and outputs one of them according to a control signal SEL. For example, when the control signal SEL is 0, the multiplexer outputs the signal CLK_OUT as the clock signal CLK_A. When the control signal SEL is 1, the multiplexer outputs the signal CLK_OUT as the clock signal CLK_B. However, if clock signals CLK_A and CLK_B have different voltage levels, when the multiplexer switches, the multiplexer will generate glitch signals. As shown in FIG. 2, when the control signal SEL changes the voltage level, the clock signal CLK_A is at a rising edge and the clock signal CLK_B is at low voltage level. At which time, the multiplexer will generate a pulse signal (glitch signal characterized as a dotted line) when the multiplexer switches to output different clock signals. The pulse signal causes synchronization failure or lost of data, and may even cause system failure.